EPM240简介
器件名称: EPM240
功能描述: JTAG & In-System Programmability
文件大小: 103.45KB 共10页
生产厂商: ALTERA
简 介:Chapter 3. JTAG & In-System Programmability MII51003-1.1 IEEE Std. 1149.1 (JTAG) Boundary Scan Support All MAX II devices provide Joint Test Action Group (JTAG) boundaryscan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001 specification. JTAG boundary-scan testing can only be performed at any time after VCCINT and all VCCIO banks have been fully powered and a tCONFIG amount of time has passed. MAX II devices can also use the JTAG port for in-system programming together with either the Quartus II software or hardware using Programming Object Files (.pof), JamTM Standard Test and Programming Language (STAPL) Files (.jam) or Jam Byte-Code Files (.jbc). The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The supported voltage level and standard is determined by the VCCIO of the bank where it resides. The dedicated JTAG pins reside in Bank 1 of all MAX II devices. MAX II devices support the JTAG instructions shown in Table 3–1. Table 3–1. MAX II JTAG Instructions (Part 1 of 2) JTAG Instruction SAMPLE/PRELOAD Instruction Code 00 0000 0101 Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins……
